OCR · GCSE · J277
OCR GCSE (9–1) Computer Science (J277)
Topic-by-topic keywords, key terms and definitions for precise exam language—separate from our revision checklists (topic coverage) and formula sheets (equations).
Examiner-style keywords and definitions organised by syllabus topic. Terms are tagged Essential (start here), Core (typical exam standard), and Advanced for harder distinctions — tick each row when you can recall it. Your progress is saved in this browser for this list.
OCR GCSE Computer Science (J277)
OCR GCSE (9–1) Computer Science (J277)
Aligned to OCR J277: Component 01 (Computer systems — architecture, memory & storage, networks, system security, system software, ethics) and Component 02 (Computational thinking, algorithms and programming — including Boolean logic and data representation).
Mark schemes: OCR mark schemes reward precise computing terminology — name registers exactly (PC, MAR, MDR, CIR, ACC) and quote units correctly (bits, bytes, KB, MB). Algorithm questions: trace tables and pseudocode that match OCR's Exam Reference Language. Examiner reports flag confusion between RAM/ROM, lossy/lossless, and validation/verification.
Active recall: 0 / 36 terms ticked
| Recalled | Topic | Level | Keyword | Definition |
|---|---|---|---|---|
| Systems architecture & the CPU | Essential | CPU | Central Processing Unit — fetches, decodes and executes instructions. | |
| Systems architecture & the CPU | Core | ALU | Arithmetic Logic Unit — performs calculations and logical comparisons. | |
| Systems architecture & the CPU | Core | Control Unit (CU) | Directs operations of the processor; manages the FDE cycle. | |
| Systems architecture & the CPU | Core | Cache | Small, fast memory storing frequently used instructions/data. | |
| Systems architecture & the CPU | Core | Clock speed | Number of FDE cycles per second, measured in Hz. | |
| Systems architecture & the CPU | Core | Von Neumann architecture | Shared memory for instructions and data; CPU with registers. | |
| Systems architecture & the CPU | Advanced | Registers (PC, MAR, MDR, CIR, ACC) | Program Counter, Memory Address/Data Registers, Current Instruction Register, Accumulator. | |
| Systems architecture & the CPU | Advanced | Fetch–decode–execute cycle | PC supplies address to MAR; instruction loaded to MDR then CIR; decoded and executed; PC increments. | |
| Memory, storage & data representation | Essential | RAM | Volatile primary memory holding currently running programs and data. | |
| Memory, storage & data representation | Essential | ROM | Non-volatile memory holding boot/firmware instructions. | |
| Memory, storage & data representation | Core | Virtual memory | Section of secondary storage used as RAM when RAM is full. | |
| Memory, storage & data representation | Core | Secondary storage (HDD/SSD/optical) | Non-volatile long-term storage — capacity, speed and durability vary. | |
| Memory, storage & data representation | Core | Binary / hexadecimal | Base 2 and base 16 — convert via grouping 4 bits per hex digit. | |
| Memory, storage & data representation | Core | Two's complement | Binary representation of signed integers — flip bits and add 1 to negate. | |
| Memory, storage & data representation | Core | ASCII / Unicode | Character encoding standards — Unicode supports more characters using more bits. | |
| Memory, storage & data representation | Advanced | Image file size | width × height × bit depth ÷ 8 (bytes). | |
| Memory, storage & data representation | Advanced | Sound sample rate / bit depth | Samples per second × bit depth × duration ÷ 8 (bytes). | |
| Networks, topologies & protocols | Core | LAN / WAN | Local Area Network (single site) vs Wide Area Network (geographically dispersed). | |
| Networks, topologies & protocols | Core | Star topology | All devices connect to a central switch — robust to single-cable failure. | |
| Networks, topologies & protocols | Core | Mesh topology | Devices interconnected with multiple paths — high reliability, high cost. | |
| Networks, topologies & protocols | Core | Packet switching | Data split into packets routed independently and reassembled. | |
| Networks, topologies & protocols | Core | TCP/IP | Suite governing reliable transport and routing across networks. | |
| Networks, topologies & protocols | Core | HTTP / HTTPS | Web request protocol; HTTPS adds TLS encryption. | |
| Networks, topologies & protocols | Advanced | DNS | Translates domain names to IP addresses via hierarchical lookup. | |
| Algorithms & complexity | Core | Linear search | Check each element in turn — works on unsorted lists; O(n). | |
| Algorithms & complexity | Core | Binary search | Repeatedly halve a sorted list; O(log n). | |
| Algorithms & complexity | Core | Bubble sort | Repeatedly swap adjacent out-of-order pairs — simple but slow. | |
| Algorithms & complexity | Core | Insertion sort | Build sorted portion by inserting each new item into place. | |
| Algorithms & complexity | Advanced | Merge sort | Divide-and-conquer — split, sort, merge; more efficient on large data. | |
| Programming & Boolean logic | Essential | Variable | Named memory location holding a value that can change. | |
| Programming & Boolean logic | Core | Sequence, selection, iteration | Three programming constructs — order, IF/ELSE, loops. | |
| Programming & Boolean logic | Core | Data types (integer, real, Boolean, char, string) | Categories controlling how data is stored and operated on. | |
| Programming & Boolean logic | Core | Procedure vs function | Subroutine without return vs subroutine returning a value. | |
| Programming & Boolean logic | Core | AND / OR / NOT | Core logic gates — used in truth tables and conditions. | |
| Programming & Boolean logic | Advanced | NAND gate | NOT AND — output false only when both inputs true. | |
| Programming & Boolean logic | Advanced | Truth table | Lists every input combination and resulting output for a logic expression. |
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