- RISC vs CISC
Two design philosophies: keep instructions simple (RISC) or powerful (CISC).
Processor designers face a choice: make each instruction simple and fast, or complex and powerful.
| RISC (Reduced Instruction Set Computer) | CISC (Complex Instruction Set Computer) | |
|---|---|---|
| Instruction set | small, simple | large, complex |
| Instruction length | fixed | variable |
| Cycles per instruction | ≈ one | often many |
| Registers | many | fewer |
| Pipelining | easy (uniform instructions) | harder |
| Where the work goes | compiler does more | hardware does more |
Interrupt handling differs:
- RISC: instructions are short and uniform, so the processor reaches a 'safe' point to service an interrupt quickly; with many registers (or register windows) the context can be saved/restored efficiently.
- CISC: a long, multi-cycle instruction may be part-way through when an interrupt arrives, which is more complex to handle — the processor must decide how to pause and resume it safely.
- RISC: few simple fixed-length instructions, many registers, relies on pipelining.
- CISC: many complex variable-length instructions, fewer registers.
- RISC moves work to the compiler; CISC to the hardware.
- RISC interrupts are simpler/faster; CISC must handle mid-instruction interrupts.
See the full worked example for processors, parallel processing and virtual machines →