Why is "Writing (A.B)' = A'.B' (keeping the AND) instead of (A.B)' = A' + B'." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Students invert each variable but forget that the operator itself must also change. How to avoid it: Memorise the rule 'break the bar, change the sign': under De Morgan, AND becomes OR and OR becomes AND. Always swap the operator as well as inverting the terms. Source: 9618 Paper 3 examiner reports — recurring De Morgan error

Why is "Labelling K-map rows/columns in binary order (00, 01, 10, 11) instead of Gray code (00, 01, 11, 10)." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Binary counting feels natural, but it breaks the single-variable adjacency the map relies on. How to avoid it: Always write the headers in Gray code so neighbouring cells differ by one bit. Then groups of adjacent 1s correspond to valid simplifications.

Why is "Making K-map groups of three (or other non-power-of-two sizes), or groups that are too small." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Students circle whatever cluster of 1s they see rather than following the grouping rules. How to avoid it: Groups must contain 1, 2, 4, 8 … cells (a power of two) and should be as LARGE as possible; overlapping groups are allowed and help make groups bigger.

Why is "Putting Carry = 1 on the 01 and 10 rows of a half adder truth table." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Confusing 'a 1 is present' with 'a carry is generated'. How to avoid it: A carry only occurs when 1 + 1 = 10. So Carry = A.B is 1 only on the 11 row; Sum = A XOR B is 1 on the 01 and 10 rows.

Why is "Forgetting the hold state (S=R=0) or not labelling S=R=1 as forbidden in an SR flip-flop." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Students focus on set and reset and overlook the two 'special' rows that define a flip-flop's behaviour. How to avoid it: Always describe all four rows: set, reset, HOLD (S=R=0), and FORBIDDEN/invalid (S=R=1). The hold state is what makes it a storage element.

Why is "Getting the middle rows (011, 101, 110) of the full adder truth table wrong." a common mistake in Boolean Algebra and Logic Circuits?

Why it happens: Adding three bits by eye is error-prone, especially when two of the three are 1. How to avoid it: Use the rule 'Sum = 1 when an ODD number of inputs are 1; Cout = 1 when TWO or more inputs are 1', then check every row against it.

Cambridge International A Levels Computer Science (9618)

Boolean Algebra and Logic Circuits

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Detailed Study Notes

Detailed notes on Hardware and Virtual Machines for Cambridge International A Levels Computer Science, covering key concepts, explanations, examples, and exam-focused revision points.

Boolean Algebra & Logic Circuits — Cambridge AS & A Level Computer Science 9618 Study Notes (2027-2029)

The A-Level logic toolkit: truth tables for half adders and full adders, SR and JK flip-flops as 1-bit stores, simplifying expressions with Boolean algebra and De Morgan's laws, and minimising logic with Karnaugh maps. Paper 3 content — every method here is done by hand (no calculator).

At a glance

Notation used here: A.B = AND, A+B = OR, A' = NOT A.
Half adder: Sum = A XOR B, Carry = A.B (adds two bits).
Full adder: adds A, B and a carry-in; Sum = A XOR B XOR Cin.
Flip-flops (SR, JK) store 1 bit — the building block of registers/SRAM.
SR flip-flop: S=1,R=0→set; S=0,R=1→reset; S=R=0→hold; S=R=1 = invalid.
JK flip-flop fixes SR's invalid state: J=K=1 toggles the output.
De Morgan's laws: (A.B)' = A'+B' and (A+B)' = A'.B'.
Karnaugh maps use Gray-code order so you can group 1s (in powers of two) to simplify.

What you’ll learn

Mapped to the Cambridge International A Level 9618 syllabus (2027-2029).

15.2 — Produce truth tables for logic circuits including half adders and full adders (may include gates with more than two inputs).
15.2 — Show understanding of a flip-flop (SR, JK): draw a logic circuit and derive a truth table; understand its role as a data storage element.
15.2 — Show understanding of Boolean algebra including De Morgan's laws; perform Boolean algebra and simplify a logic circuit/expression.
15.2 — Show understanding of Karnaugh maps (K-maps): understand their benefits and solve logic problems using them.

Half adders and full adders

Circuits that add binary digits and produce a sum and a carry.

Adders are circuits that perform binary addition.

Half adder — adds two single bits A and B, producing a Sum and a Carry:

$\text{Sum} = A \oplus B \qquad \text{Carry} = A.B$

(⊕ means XOR.) It is built from one XOR gate (Sum) and one AND gate (Carry):

A	B	Sum	Carry
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

Full adder — adds three bits: A, B and a carry-in (Cin), giving a Sum and a carry-out (Cout):

$\text{Sum} = A \oplus B \oplus C_{in} \qquad C_{out} = A.B + C_{in}.(A \oplus B)$

Full adders can be chained so each carry-out feeds the next column's carry-in — this is how a processor adds multi-bit numbers.

Half adder: Sum = A XOR B, Carry = A.B (two inputs).
Full adder: adds A, B, Cin → Sum and Cout (three inputs).
Sum = A XOR B XOR Cin; Cout = A.B + Cin.(A XOR B).
Chained full adders add multi-bit numbers.

See the full worked example for boolean algebra and logic circuits →

Flip-flops (SR and JK)

1-bit memory cells — the basis of registers and SRAM.

A flip-flop is a circuit that stores one bit (it has two stable states), making it a fundamental data storage element. Registers and SRAM are built from flip-flops.

SR flip-flop — built from two cross-coupled NOR (or NAND) gates, with inputs S (Set) and R (Reset) and output Q:

S	R	Q (next)	Meaning
0	0	Q (unchanged)	hold the stored bit
0	1	0	reset to 0
1	0	1	set to 1
1	1	—	invalid / forbidden

The S=R=1 input is not allowed because it drives the outputs into an undefined/unstable state.

JK flip-flop — refines the SR design so that the forbidden input becomes useful: when J=K=1 the output toggles (flips to its opposite). This removes the invalid state, which is why JK flip-flops are widely used (e.g. in counters).

Flip-flop = stores 1 bit (basis of registers/SRAM).
SR: set (1,0), reset (0,1), hold (0,0), invalid (1,1).
JK fixes the invalid state: J=K=1 toggles Q.
Drawn from cross-coupled NOR/NAND gates.

See the full worked example for boolean algebra and logic circuits →

Boolean algebra and De Morgan's laws

Algebraic rules to simplify logic expressions and circuits.

Boolean algebra lets you simplify an expression (and therefore its circuit) so it uses fewer gates — cheaper, faster and easier to build.

Key identities (with A.B = AND, A+B = OR, A' = NOT A):

Rule	Form
Identity	A+0 = A; A.1 = A
Null	A+1 = 1; A.0 = 0
Idempotent	A+A = A; A.A = A
Complement	A+A' = 1; A.A' = 0
Absorption	A + A.B = A; A.(A+B) = A
Distributive	A.(B+C) = A.B + A.C

De Morgan's laws (essential — they let you break a NOT over a bracket):

$(A.B)' = A' + B' \qquad (A+B)' = A'.B'$

In words: 'break the bar, change the sign' — NOT of an AND becomes OR of the NOTs, and NOT of an OR becomes AND of the NOTs.

Example: simplify $(A + B').B$ = A.B + B'.B (distributive) = A.B + 0 (B'.B = 0) = A.B.

Simplifying = fewer gates → cheaper/faster circuits.
Learn identity, null, idempotent, complement, absorption, distributive.
De Morgan: (A.B)' = A'+B'; (A+B)' = A'.B'.
'Break the bar, change the sign.'

See the full worked example for boolean algebra and logic circuits →

Karnaugh maps (K-maps)

A grid method to minimise a Boolean expression visually.

A Karnaugh map is a grid that makes simplification visual and reliable — often faster and less error-prone than algebra.

How it works:

Draw a grid with one cell per row of the truth table. Label rows/columns in Gray-code order (00, 01, 11, 10) so that adjacent cells differ by exactly one variable.
Write each output (0/1) into its cell.
Group the 1s into rectangular groups whose size is a power of two (1, 2, 4, 8…). Groups may overlap and wrap around the edges. Make groups as large as possible (and use as few as possible).
Each group becomes one simplified product term (the variables that stay constant across the group); OR the terms together (sum of products).

Benefit: a K-map gives a guaranteed minimal sum-of-products without long algebra, and the Gray-code ordering is what makes neighbouring 1s combine correctly.

One cell per truth-table row; label in Gray code (00,01,11,10).
Group 1s in powers of two; groups can overlap and wrap.
Bigger groups = simpler terms; use as few groups as possible.
Each group → one product term; OR them (sum of products).

See the full worked example for boolean algebra and logic circuits →

Quick recap

Half adder: Sum = A XOR B, Carry = A.B; full adder also takes a carry-in.
Full adder Sum = A XOR B XOR Cin; Cout = A.B + Cin.(A XOR B); chain them for multi-bit addition.
Flip-flops store 1 bit; SR has an invalid S=R=1 state; JK toggles when J=K=1.
Boolean algebra simplifies expressions → fewer gates.
De Morgan: (A.B)' = A'+B'; (A+B)' = A'.B' — change operator AND complement terms.
Karnaugh maps use Gray-code order; group 1s in powers of two for a minimal sum of products.

Memorise this

Verbatim phrases and definitions Cambridge mark schemes credit.

Half adder: Sum = A XOR B, Carry = A.B.
Full adder: Sum = A XOR B XOR Cin; Cout = A.B + Cin.(A XOR B).
SR flip-flop forbidden input: S=1, R=1.
JK flip-flop: J=K=1 toggles the output.
De Morgan: (A.B)' = A'+B' ; (A+B)' = A'.B'.
K-map axes use Gray code (00,01,11,10); group 1s in powers of two.

How it’s examined

Section 15.2 is A-Level content assessed in Paper 3 (Advanced Theory, 1 h 30 min, 75 marks) — written, externally assessed, no calculator. Expect: complete a truth table for a half/full adder or a flip-flop, draw a flip-flop circuit, simplify an expression using Boolean algebra and De Morgan's laws (show every step), and minimise a function with a Karnaugh map (show your groups). Always show working — method marks are available, and a stated wrong final term with correct grouping can still score.

Sources: Cambridge International AS & A Level Computer Science 9618 syllabus (2027-2029), section 15.2. Last reviewed 2026-06-21.

Take this whole topic with you

Step-by-step worked examples — Boolean Algebra and Logic Circuits

Step-by-step solutions to past-paper-style questions on boolean algebra and logic circuits, written exactly the way a tutor would explain them at the board.

Question type:

1Truth table for a half adder
Getting startedGraph or diagram• 9618 Paper 3 style• half adder, truth table, XOR, AO2
Question
A half adder adds two single binary digits A and B, producing a Sum bit and a Carry bit. Complete the truth table for the half adder and state the Boolean expressions for Sum and Carry. (4 marks)
Step-by-step solution
1. Step 1
  A half adder has two inputs (A and B) so the truth table has 2^2 = 4 rows. List the input combinations in binary order 00, 01, 10, 11.
2. Step 2
  Add the two bits like ordinary binary addition. 0+0 = 0 (Sum 0, Carry 0). 0+1 = 1 (Sum 1, Carry 0). 1+0 = 1 (Sum 1, Carry 0). 1+1 = 10 in binary, which is Sum 0 with a Carry of 1.
3. Step 3
  Write the completed truth table.
  $\begin{array}{c}\textbf{See markdown table below}\end{array}$
4. Step 4
  Read the pattern off the columns. The Sum column is 1 only when A and B differ — that is XOR. The Carry column is 1 only when both are 1 — that is AND.
  $\text{Sum} = A \oplus B \qquad \text{Carry} = A.B$
Answer
Truth table:

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Sum = A XOR B (written A ⊕ B); Carry = A.B. The half adder is built from one XOR gate (Sum) and one AND gate (Carry).
Examiner tip
All four output bits correct earns the table marks; the two expression marks need both Sum = A⊕B and Carry = A.B. A very common slip is putting Carry = 1 on the 01 and 10 rows — there is no carry unless BOTH inputs are 1.
2SR flip-flop circuit and truth table
Getting startedGraph or diagram• 9618 Paper 3 style• flip-flop, SR, storage, NOR, AO1
Question
An SR flip-flop is built from two cross-coupled NOR gates with inputs S (Set) and R (Reset) and output Q. Describe the output produced for each input combination, identify the forbidden state, and explain why a flip-flop is described as a storage element. (5 marks)
Step-by-step solution
1. Step 1
  Two NOR gates are cross-coupled: the output of each NOR feeds back into the input of the other. This feedback is what lets the circuit 'remember' a value.
2. Step 2
  Apply S = 1, R = 0: the flip-flop is SET, so Q becomes 1. Apply S = 0, R = 1: the flip-flop is RESET, so Q becomes 0.
  $S=1,R=0 \Rightarrow Q=1 \qquad S=0,R=1 \Rightarrow Q=0$
3. Step 3
  Apply S = 0, R = 0: neither set nor reset is active, so the output HOLDS its previous value — this is the memory (storage) state.
4. Step 4
  Apply S = 1, R = 1: this tries to set and reset at the same time. It drives both outputs the same way and is unstable when the inputs return to 0, so it is the forbidden / invalid state.
5. Step 5
  Because the circuit holds Q when S = R = 0, it stores one bit indefinitely. Many flip-flops together form registers and the cells of SRAM — that is why a flip-flop is a 1-bit data storage element.
Answer

S R Q (output)
0 0 Q holds (no change)
0 1 0 (reset)
1 0 1 (set)
1 1 Invalid / forbidden

S=R=0 holds the stored bit, which is why the SR flip-flop is a 1-bit storage element (the building block of registers and SRAM). S=R=1 is forbidden because the behaviour is undefined when the inputs return to 0.
Examiner tip
State the four cases precisely. The hold state (S=R=0) is the one weak answers forget, yet it is the whole point of a flip-flop. Note 'forbidden' for S=R=1, not merely 'both outputs 1'.
3Truth table for a full adder
Building confidenceMulti-step problem• 9618 Paper 3 style• full adder, truth table, carry in, AO2
Question
A full adder adds three inputs: A, B and a carry-in Cin. It outputs a Sum bit and a carry-out Cout. Complete the eight-row truth table and give the Boolean expressions for Sum and Cout. (6 marks)
Step-by-step solution
1. Step 1
  Three inputs means 2^3 = 8 rows. List A B Cin in binary order from 000 to 111.
2. Step 2
  For each row add the three bits. The Sum bit is 1 when an ODD number of inputs are 1; the carry-out is 1 when TWO OR MORE inputs are 1.
3. Step 3
  Work through each row. 000→Sum0 Cout0; 001→Sum1 Cout0; 010→Sum1 Cout0; 011→Sum0 Cout1; 100→Sum1 Cout0; 101→Sum0 Cout1; 110→Sum0 Cout1; 111→Sum1 Cout1.
4. Step 4
  Sum is 1 for an odd count of 1s, which is the three-input XOR. Cout is 1 when at least two inputs are 1, which simplifies to (A.B) + (Cin.(A XOR B)).
  $\text{Sum} = A \oplus B \oplus C_{in} \qquad C_{out} = (A.B) + (C_{in}.(A \oplus B))$
Answer

A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Sum = A ⊕ B ⊕ Cin; Cout = (A.B) + (Cin.(A ⊕ B)). A full adder is two half adders plus an OR gate.
Examiner tip
Half the marks are for the eight rows being correct. The reliable check is 'Sum = 1 for an odd number of input 1s' and 'Cout = 1 when two or more inputs are 1'. Many candidates muddle the 011, 101 and 110 rows — verify each against that rule.
4Apply De Morgan, simplify, and verify by truth table
Building confidenceShow that / prove• 9618 Paper 3 style• De Morgan, simplification, truth table, AO2
Question
Simplify the expression (A.B)' + A to its simplest form, showing each step and naming the law used at each stage. Then verify your simplified answer by constructing a truth table. (6 marks)
Step-by-step solution
1. Step 1
  Apply De Morgan's law to (A.B)'. The law states (A.B)' = A' + B'.
  $(A.B)' + A = (A' + B') + A$
2. Step 2
  Reorder using the commutative and associative laws to bring the A terms together.
  $= (A + A') + B'$
3. Step 3
  Apply the complement law A + A' = 1.
  $= 1 + B'$
4. Step 4
  Apply the identity 1 + X = 1 (anything OR 1 is 1). The simplified result is 1.
  $= 1$
5. Step 5
  Verify by truth table. Build columns for A.B, then (A.B)', then (A.B)' + A, and check the final column matches the simplified answer (a constant 1) for every input combination.
  $\text{All four rows of }(A.B)'+A \text{ equal } 1 = \text{simplified result}$
Answer
(A.B)' + A = 1 (the expression is always true).

Verification truth table:

A B A.B (A.B)' (A.B)' + A
0 0 0 1 1
0 1 0 1 1
1 0 0 1 1
1 1 1 0 1

The final column is 1 in every row, which matches the simplified result of 1 — so the simplification is confirmed.
Examiner tip
Marks: correct De Morgan expansion (A.B)' = A' + B' (1); complement A + A' = 1 (1); identity 1 + B' = 1 and final answer 1 (1-2); a correctly built truth table whose final column is all 1s, matching the answer (2). The frequent error is writing (A.B)' = A'.B' — that is the WRONG law; when the bar breaks, AND becomes OR (and OR becomes AND).
5Simplify using Boolean identities
StretchShow that / prove• 9618 Paper 3 style• Boolean algebra, absorption, distributive, AO2
Question
Simplify the Boolean expression A.B + A.B' + A'.B to its simplest form, naming the laws used. (5 marks)
Step-by-step solution
1. Step 1
  Factor A out of the first two terms using the distributive law.
  $A.B + A.B' + A'.B = A.(B + B') + A'.B$
2. Step 2
  Apply the complement law B + B' = 1.
  $= A.1 + A'.B$
3. Step 3
  Apply the identity A.1 = A.
  $= A + A'.B$
4. Step 4
  Apply the absorption variant A + A'.B = A + B (because the A' term only adds new coverage where A is 0, i.e. the B cases).
  $= A + B$
Answer
A.B + A.B' + A'.B = A + B.
Examiner tip
Each named law is worth a mark, so show every step rather than jumping to the answer. The trickiest step is A + A'.B = A + B — quote it explicitly. You can verify by truth table: A+B is 1 in three of the four rows, exactly matching the original expression.
6Minimise a 4-variable function with a Karnaugh map
StretchGraph or diagram• 9618 Paper 3 style• Karnaugh map, K-map, sum of products, grouping, AO2
Question
A function F of four variables A, B, C, D is 1 for the minterms 2, 3, 6, 7, 10, 11, 12, 13, 14, 15 (where the minterm number is the binary value ABCD, A most significant) and 0 for all other inputs. Draw the Karnaugh map, group the 1s, and write the simplified sum-of-products expression for F, explaining each group. (6 marks)
Step-by-step solution
1. Step 1
  Draw a 4x4 K-map. Label the rows with AB and the columns with CD, both in Gray-code order 00, 01, 11, 10, so that any two adjacent cells (including the wrap-around edges) differ by exactly one variable.
2. Step 2
  Enter a 1 in every cell whose minterm number is in the list. Minterm m = ABCD in binary: e.g. m=12 is A=1,B=1,C=0,D=0; m=2 is A=0,B=0,C=1,D=0. Filling all ten gives the grid below.
  $\begin{array}{c|cccc} \text{AB}\backslash\text{CD} & 00 & 01 & 11 & 10 \\ \hline 00 & 0 & 0 & 1 & 1 \\ 01 & 0 & 0 & 1 & 1 \\ 11 & 1 & 1 & 1 & 1 \\ 10 & 0 & 0 & 1 & 1 \end{array}$
3. Step 3
  Find the largest power-of-two groups. The two right-hand columns (CD = 11 and CD = 10) are all 1s — that is a block of EIGHT cells. Across all eight cells only C stays constant at 1 (A, B and D all vary), so this group eliminates A, B and D and leaves the single term C.
  $\text{group of 8 (CD}=11,10) \Rightarrow C$
4. Step 4
  The remaining uncovered 1s are in the AB = 11 row at CD = 00 and CD = 01 (minterms 12 and 13). Group the whole AB = 11 row — a block of FOUR. Across that row A = 1 and B = 1 stay constant while C and D vary, so it eliminates C and D and gives the term A.B. (Overlap with the group of 8 is allowed and keeps the groups as large as possible.)
  $\text{group of 4 (AB}=11) \Rightarrow A.B$
5. Step 5
  OR the two group terms together to get the minimal sum-of-products. Larger groups remove more variables, so the group of 8 collapses to one literal (C) and the group of 4 to two literals (A.B).
  $F = C + A.B$
Answer
F = A.B + C. The Gray-code K-map is covered by two groups: the group of EIGHT formed by the CD = 11 and CD = 10 columns (every C = 1 cell) gives the term C; the group of FOUR formed by the AB = 11 row gives the term A.B. The groups overlap on minterms 14 and 15, which is permitted because it lets each group stay as large as possible.
Examiner tip
Marks: correct Gray-code grid with the ten 1s placed (1-2); identifying the group of 8 → C (1-2); identifying the group of 4 → A.B (1); final F = A.B + C (1). Groups must be powers of two (1, 2, 4, 8, 16) and as LARGE as possible — circling a group of four where a group of eight exists loses the minimisation marks. The classic slip is labelling headers in binary 00, 01, 10, 11 instead of Gray code 00, 01, 11, 10, which destroys single-variable adjacency.

S	R	Q (output)
0	0	Q holds (no change)
0	1	0 (reset)
1	0	1 (set)
1	1	Invalid / forbidden

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

A	B	A.B	(A.B)'	(A.B)' + A
0	0	0	1	1
0	1	0	1	1
1	0	0	1	1
1	1	1	0	1

Model Answers — Boolean Algebra and Logic Circuits

High-scoring sample answers for boolean algebra and logic circuits on the Cambridge IGCSE paper, with examiner-style notes mapping each response to the mark scheme and assessment objectives.

Question 1
9618 Paper 3 style2 marks
State what is meant by a flip-flop and explain why it is described as a data storage element.
Model answer
A flip-flop is a sequential logic circuit, built from cross-coupled logic gates, that has two stable output states and can therefore store one binary digit (a 0 or a 1). It is a storage element because once set or reset it holds its output value until it is deliberately changed, so the bit it holds is remembered. Groups of flip-flops form registers and the cells of static RAM (SRAM).
Why this scores
Mark 1: stores one bit / has two stable states. Mark 2: holds (remembers) the value until changed, hence storage. Mentioning registers/SRAM shows wider understanding.
Question 2
9618 Paper 3 style2 marks
State both of De Morgan's laws using the notation A.B, A+B and A' for NOT A.
Model answer
De Morgan's first law: (A.B)' = A' + B' — the inverse of an AND is the OR of the inverses. De Morgan's second law: (A+B)' = A'.B' — the inverse of an OR is the AND of the inverses. In words: when you break the bar, AND swaps with OR and each variable is individually inverted.
Why this scores
One mark per correct law. The classic error is keeping the operator the same (writing (A.B)' = A'.B'); the operator MUST flip.
Question 3
9618 Paper 3 style4 marks
Explain the difference between a half adder and a full adder, and state why a full adder is needed to add multi-bit binary numbers.
Model answer
A half adder adds just two single bits, A and B, producing a Sum (A XOR B) and a Carry (A.B). It has no way of accepting a carry coming in from a previous (less significant) column, so it can only ever add the very first column of a binary addition. A full adder adds three bits — A, B and a carry-in Cin — producing a Sum (A XOR B XOR Cin) and a carry-out Cout = (A.B) + (Cin.(A XOR B)). When adding multi-bit numbers, every column after the first may receive a carry from the column to its right, so each of those columns must be handled by a full adder; the carry-out of one stage becomes the carry-in of the next. A chain of full adders (a ripple-carry adder) therefore lets the hardware add numbers of any width.
Why this scores
Marks for: half adder = 2 inputs, no carry-in; full adder = 3 inputs incl. carry-in; full adder needed because later columns receive a carry; carry-out chains into the next stage.
Question 4
9618 Paper 3 style4 marks
An SR flip-flop has a forbidden input combination. State which combination this is and explain how a JK flip-flop resolves the problem.
Model answer
In an SR flip-flop the forbidden (invalid) combination is S = 1 and R = 1, because asserting Set and Reset at the same time gives an undefined output — when both inputs then return to 0 the circuit can settle into an unpredictable state. A JK flip-flop is designed to remove this problem. It has inputs J and K that behave like Set and Reset for the J = 1, K = 0 and J = 0, K = 1 cases, and J = 0, K = 0 still holds the value. Crucially, when J = 1 and K = 1 the JK flip-flop does not become invalid — instead it TOGGLES, meaning the output Q flips to the opposite of its current value. Every input combination of the JK flip-flop is therefore well defined.
Why this scores
Marks: S=R=1 is forbidden (1); why it is undefined (1); JK uses J=K=1 productively (1); J=K=1 toggles Q so there is no invalid state (1).
Question 5
9618 Paper 3 style5 marks
Describe what a Karnaugh map is and explain the benefits of using one to simplify a Boolean expression compared with using Boolean algebra alone.
Model answer
A Karnaugh map (K-map) is a grid representation of a truth table in which the rows and columns are labelled using Gray code (for example 00, 01, 11, 10), so that physically adjacent cells differ by exactly one variable. Each cell holds the function's output (0 or 1) for one input combination. To simplify, the 1s are grouped into rectangular blocks whose size is a power of two (1, 2, 4, 8, …); each group is then written as a single product term in which any variable that changes across the group is eliminated, and the terms are ORed together to give a simplified sum-of-products expression. The benefits over plain Boolean algebra are: (1) it is systematic and visual, so you can see the adjacencies rather than having to spot algebraic factorisations; (2) it greatly reduces the chance of error, because you are not applying laws by hand; (3) larger groups directly give simpler terms, so a near-minimal result is reached quickly; and (4) it automatically handles cases that are easy to miss algebraically, such as overlapping groups and (where present) don't-care conditions.
Why this scores
Marks for: K-map = grid form of truth table with Gray-code adjacency; group 1s in powers of two; each group → product term with changing variables removed; benefit of being systematic/visual; benefit of fewer errors / larger groups = simpler terms.
Question 6
9618 Paper 3 style6 marks
A logic circuit implements F = (A + B).(A + B'). Simplify F using Boolean algebra, naming each law, and describe how the simplified circuit differs from the original.
Model answer
Start with F = (A + B).(A + B'). Apply the distributive law in the form (A + X).(A + Y) = A + X.Y, treating X = B and Y = B': this gives F = A + B.B'. Apply the complement law B.B' = 0 (a variable ANDed with its inverse is always 0): F = A + 0. Apply the identity A + 0 = A: F = A. So the whole expression simplifies to just A. In hardware terms, the original circuit needs two OR gates (one for A + B, one for A + B'), a NOT gate to produce B', and an AND gate to combine the two OR outputs — four gates and a wasted input B. The simplified circuit needs no gates at all: the output is simply the input A connected straight to F. This shows how Boolean simplification removes redundant gates, reducing cost, power consumption and propagation delay.
Why this scores
Marks: distributive step (1); complement B.B'=0 (1); identity A+0=A (1); final F=A (1); original gate count described (1); simplified circuit = direct connection of A, with a comment on fewer gates (1).

Key Definitions and Keywords — Boolean Algebra and Logic Circuits

Definitions to memorise and the exact keywords mark schemes credit for boolean algebra and logic circuits answers — sharpened from recent examiner reports for the 2026 Cambridge IGCSE sitting.

Half adder
Examiner keyword
A combinational logic circuit that adds two single binary digits A and B, producing a Sum bit and a Carry bit. Sum = A XOR B and Carry = A.B. It cannot accept a carry-in.
Example
Built from one XOR gate (Sum) and one AND gate (Carry).
Related: Full adder, Sum, Carry
Full adder
Examiner keyword
A combinational logic circuit that adds three binary digits A, B and a carry-in Cin, producing a Sum bit and a carry-out Cout. Sum = A XOR B XOR Cin and Cout = (A.B) + (Cin.(A XOR B)).
Example
A full adder can be built from two half adders plus an OR gate; chaining full adders adds multi-bit numbers.
Related: Half adder, Carry, Sum
Sum (in an adder)
The least-significant output bit of an adder — the result digit kept in the current column. It equals A XOR B for a half adder and A XOR B XOR Cin for a full adder.
Example
Adding 1 + 1 gives Sum 0 with a Carry of 1.
Related: Carry, Half adder, Full adder
Carry
Examiner keyword
The output bit that is passed to the next, more significant column when an addition overflows a single column. Carry = A.B in a half adder; the carry-out of one full adder becomes the carry-in of the next.
Related: Sum, Full adder
Flip-flop
Examiner keyword
A sequential logic circuit, made from cross-coupled gates, with two stable output states. It stores one binary digit and holds it until deliberately changed, so it acts as a 1-bit data storage element.
Example
Groups of flip-flops form registers and the cells of SRAM.
Related: SR flip flop, JK flip flop
SR flip-flop
Examiner keyword
A flip-flop with Set (S) and Reset (R) inputs, typically built from two cross-coupled NOR (or NAND) gates. S=1,R=0 sets Q to 1; S=0,R=1 resets Q to 0; S=0,R=0 holds the value; S=1,R=1 is forbidden (invalid).
Related: Flip flop, JK flip flop
JK flip-flop
Examiner keyword
An improved flip-flop with inputs J and K that removes the forbidden state of the SR flip-flop. J=1,K=0 sets, J=0,K=1 resets, J=0,K=0 holds, and J=1,K=1 toggles (inverts) the output Q.
Related: SR flip flop, Flip flop
Boolean algebra
Examiner keyword
The algebra of logic, in which variables take the value 0 or 1 and the operators are AND (.), OR (+) and NOT ('). Its identities are used to simplify logic expressions and circuits.
Example
A + A.B = A (absorption); A + A' = 1 (complement).
Related: De Morgan's laws, Sum of products
De Morgan's laws
Examiner keyword
Two laws for inverting compound expressions: (A.B)' = A' + B' and (A+B)' = A'.B'. When the bar 'breaks', AND swaps with OR and each variable is inverted.
Example
(A.B)' simplifies to A' + B', not A'.B'.
Related: Boolean algebra
Karnaugh map (K-map)
Examiner keyword
A grid form of a truth table with rows/columns ordered in Gray code, so adjacent cells differ by one variable. Grouping the 1s into power-of-two blocks yields a simplified sum-of-products expression.
Example
A 2-variable K-map has 4 cells; a 4-variable K-map has 16 cells.
Related: Sum of products, Boolean algebra
Sum of products (SOP)
Examiner keyword
A Boolean expression written as several AND (product) terms ORed (summed) together, e.g. A.B' + A'.B. This is the standard form produced when simplifying with a Karnaugh map.
Example
F = A + B is a (minimal) sum-of-products expression.
Related: Karnaugh map, Boolean algebra
Gray code (in a K-map)
An ordering such as 00, 01, 11, 10 in which successive values differ by exactly one bit. Using it to label a K-map ensures neighbouring cells differ by a single variable, which is what makes grouping valid.
Example
K-map columns are labelled 00, 01, 11, 10 — never 00, 01, 10, 11.
Related: Karnaugh map
Truth table
A table listing every possible combination of inputs and the resulting output(s) of a logic circuit. An n-input circuit has 2^n rows, listed in binary order.
Example
A full adder has three inputs, so its truth table has 2^3 = 8 rows.
Related: Half adder, Full adder

Common Mistakes and Misconceptions — Boolean Algebra and Logic Circuits

The traps other students keep falling into on boolean algebra and logic circuits questions — taken from recent Cambridge IGCSE examiner reports and mark schemes — and how to avoid them.

✕Writing (A.B)' = A'.B' (keeping the AND) instead of (A.B)' = A' + B'.
9618 Paper 3 examiner reports — recurring De Morgan error
Why it happens
Students invert each variable but forget that the operator itself must also change.
How to avoid it
Memorise the rule 'break the bar, change the sign': under De Morgan, AND becomes OR and OR becomes AND. Always swap the operator as well as inverting the terms.
✕Labelling K-map rows/columns in binary order (00, 01, 10, 11) instead of Gray code (00, 01, 11, 10).
Why it happens
Binary counting feels natural, but it breaks the single-variable adjacency the map relies on.
How to avoid it
Always write the headers in Gray code so neighbouring cells differ by one bit. Then groups of adjacent 1s correspond to valid simplifications.
✕Making K-map groups of three (or other non-power-of-two sizes), or groups that are too small.
Why it happens
Students circle whatever cluster of 1s they see rather than following the grouping rules.
How to avoid it
Groups must contain 1, 2, 4, 8 … cells (a power of two) and should be as LARGE as possible; overlapping groups are allowed and help make groups bigger.
✕Putting Carry = 1 on the 01 and 10 rows of a half adder truth table.
Why it happens
Confusing 'a 1 is present' with 'a carry is generated'.
How to avoid it
A carry only occurs when 1 + 1 = 10. So Carry = A.B is 1 only on the 11 row; Sum = A XOR B is 1 on the 01 and 10 rows.
✕Forgetting the hold state (S=R=0) or not labelling S=R=1 as forbidden in an SR flip-flop.
Why it happens
Students focus on set and reset and overlook the two 'special' rows that define a flip-flop's behaviour.
How to avoid it
Always describe all four rows: set, reset, HOLD (S=R=0), and FORBIDDEN/invalid (S=R=1). The hold state is what makes it a storage element.
✕Getting the middle rows (011, 101, 110) of the full adder truth table wrong.
Why it happens
Adding three bits by eye is error-prone, especially when two of the three are 1.
How to avoid it
Use the rule 'Sum = 1 when an ODD number of inputs are 1; Cout = 1 when TWO or more inputs are 1', then check every row against it.

Boolean Algebra and Logic Circuits

Detailed Study Notes

At a glance

What you’ll learn

Quick recap

Memorise this

How it’s examined

Take this whole topic with you

1Truth table for a half adder

2SR flip-flop circuit and truth table

3Truth table for a full adder

4Apply De Morgan, simplify, and verify by truth table

5Simplify using Boolean identities

6Minimise a 4-variable function with a Karnaugh map

Half adder

Full adder

Sum (in an adder)

Carry

Flip-flop

SR flip-flop

JK flip-flop

Boolean algebra

De Morgan's laws

Karnaugh map (K-map)

Sum of products (SOP)

Gray code (in a K-map)

Truth table

✕Writing (A.B)' = A'.B' (keeping the AND) instead of (A.B)' = A' + B'.

✕Labelling K-map rows/columns in binary order (00, 01, 10, 11) instead of Gray code (00, 01, 11, 10).

✕Making K-map groups of three (or other non-power-of-two sizes), or groups that are too small.

✕Putting Carry = 1 on the 01 and 10 rows of a half adder truth table.

✕Forgetting the hold state (S=R=0) or not labelling S=R=1 as forbidden in an SR flip-flop.

✕Getting the middle rows (011, 101, 110) of the full adder truth table wrong.