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Detailed notes on Hardware for Cambridge IGCSE Computer Science, covering key concepts, explanations, examples, and exam-focused revision points.
What's INSIDE a CPU and how it actually runs your programs. ALU, control unit, registers and buses; the Von Neumann model; the fetch-decode-execute cycle; what makes one CPU faster than another; and where embedded systems differ.
Mapped to the Cambridge IGCSE 0478 syllabus (2026-2028).
ALU does the maths; control unit conducts; registers hold the working values.
The Central Processing Unit (CPU) is the brain of the computer. It has three main parts.
1. ALU (Arithmetic and Logic Unit). Does the actual computation:
2. Control Unit (CU). Conducts the orchestra:
3. Registers. Tiny, super-fast storage locations inside the CPU. Each has a specific role:
| Register | Role |
|---|---|
| PC (Program Counter) | Address of the NEXT instruction. |
| MAR (Memory Address Register) | Holds the address being read/written. |
| MDR (Memory Data Register) | Holds the data/instruction transferred. |
| CIR (Current Instruction Register) | Holds the instruction being decoded/executed. |
| ACC (Accumulator) | Holds the result of arithmetic/logic. |
Cambridge tip. Examiner reports flag candidates who write 'memory' when they should write 'register'. They are different: registers are INSIDE the CPU and orders of magnitude faster than RAM.
Instructions and data share the same memory and the same buses.
Almost every general-purpose computer follows the Von Neumann architecture. The key idea: instructions and data are stored in the SAME main memory and accessed via the SAME buses.
The buses (the wires that move signals around):
Why this design wins. It's flexible — the same memory holds your operating system, your spreadsheet's code AND the spreadsheet's data. Programs can be loaded, modified and replaced without redesigning the hardware.
The downside ('Von Neumann bottleneck'). Because instructions and data share one bus, the CPU sometimes has to wait. Modern CPUs hide this with caches and pipelining (more on those below).
Cambridge tip. Mark scheme rewards naming the THREE buses and stating that instructions and data share memory.
Three stages, repeated billions of times per second.
Every instruction the CPU executes goes through three stages — the fetch-decode-execute (FDE) cycle.
FETCH.
DECODE. The control unit decodes the instruction in the CIR — interprets the opcode and operand to figure out what action is needed and which components to involve.
EXECUTE. The control unit signals the ALU and registers to perform the operation. The result may be stored in the accumulator or written back to memory (which would trigger another address-and-data-bus exchange).
The cycle then repeats — billions of times per second on a modern CPU.
Cambridge tip. Top-band answers walk through the buses and registers explicitly. 'It fetches the instruction and runs it' scores 1 of 6.
Three big levers: clock speed, cores, cache.
A CPU's performance depends on more than one factor. The big three:
Clock speed. Measured in hertz (Hz, GHz). One full clock cycle drives one step of the FDE cycle. Higher clock speed = more instructions per second, all else being equal.
Number of cores. Each core is a self-contained processor that can run its own FDE cycle. A quad-core CPU can run FOUR programs simultaneously, or split a multi-threaded program across cores. (Single-threaded programs only see one core's worth of speed.)
Cache size. Cache is fast on-chip memory holding frequently-used data and instructions. Trips to cache take a single cycle; trips to RAM take dozens. More cache = fewer waits.
Other factors.
Why this matters in real life. A 3.5 GHz dual-core can be SLOWER than a 2.5 GHz octa-core for software designed to use multiple threads (video editing, modern games). When buying a computer, balance all three.
Embedded = dedicated to one job, built into another device.
An embedded system is a computer built into a larger device, dedicated to a SPECIFIC task. The user usually doesn't think of it as a 'computer' at all.
Examples of embedded systems:
Compared to a general-purpose computer:
| Embedded system | General-purpose | |
|---|---|---|
| Purpose | One specific task | Runs many programs |
| Hardware | Microcontroller, low power, low cost | Powerful CPU, lots of RAM |
| Software | Firmware in ROM/flash | OS + many applications |
| User interaction | Limited (buttons, dials, display) | Keyboard, mouse, screen |
| Updates | Rare; via service intervention | Frequent; user-initiated |
The key word is DEDICATED. A smartphone runs many apps via an OS — it's general-purpose. A car ECU only runs the engine code — embedded.
Cambridge tip. Mark scheme expects students to say 'designed for a specific task / dedicated' and 'built into another device'.
Verbatim phrases and definitions Cambridge mark schemes credit.
Computer architecture appears on roughly half of Paper 1s. Most-tested questions: describe the FDE cycle (6-8 marks), factors affecting CPU performance (4-6 marks), embedded vs general-purpose (4-6 marks). Examiner reports flag the FDE cycle as the question candidates lose most marks on — for vagueness rather than wrong answers.
Sources: Cambridge IGCSE Computer Science 0478 syllabus (2026-2028); 0478 Examiner Reports 2022-2024; 0478/12 Oct/Nov 2023 question paper and mark scheme. Last reviewed 2026-05-09.
Step-by-step solutions to past-paper-style questions on computer architecture, written exactly the way a tutor would explain them at the board.
Question
State the purpose of the CPU in a computer system and name TWO components found inside it. (2 marks)
Step-by-step solution
Step 1
Purpose (1 mark). The CPU (Central Processing Unit) processes data and instructions — it fetches, decodes and executes the instructions that make up a program. It is often called the 'brain' of the computer, but for the mark write 'processes instructions/data'.
Step 2
Components (1 mark). Name any two from: ALU (Arithmetic and Logic Unit), Control Unit (CU), registers (e.g. PC, MAR, MDR, CIR, accumulator). One mark for two correctly named parts.
Answer
Purpose: processes (fetches, decodes and executes) instructions and data. Two components: the ALU and the Control Unit (registers also accepted).
Examiner tip
Keep it tight on 'state' questions — one short phrase for the purpose, then two named parts. 'Stores files' describes storage, not the CPU, and scores 0.
Question
A register is a small, fast storage location inside the CPU. State the purpose of (a) the Program Counter (PC) and (b) the Memory Address Register (MAR). (2 marks)
Step-by-step solution
Step 1
(a) Program Counter (1 mark). The PC holds the memory ADDRESS of the NEXT instruction to be fetched. It is incremented each cycle so the CPU steps through the program in order.
Step 2
(b) MAR (1 mark). The MAR holds the ADDRESS in memory that is currently being read from or written to. The address travels from the MAR onto the address bus.
Answer
(a) PC: holds the address of the next instruction to be fetched. (b) MAR: holds the address of the memory location currently being accessed.
Examiner tip
Both registers hold ADDRESSES — the difference is 'next instruction' (PC) vs 'currently being accessed' (MAR). Don't confuse the MAR (address) with the MDR (the actual data/instruction).
Question
Compare an embedded system with a general-purpose computer. Give one example of each. (4 marks)
Step-by-step solution
Step 1
Purpose (2 marks). An embedded system is designed for a SPECIFIC task and is built into a larger device — e.g. the controller in a washing machine, the system in a digital camera, the engine management unit in a car. A general-purpose computer can run many DIFFERENT programs — e.g. a desktop PC, a laptop.
Step 2
Hardware/software trade-off (2 marks). Embedded systems use cheaper, lower-power microcontrollers; their firmware is fixed (or rarely updated) and lives in ROM/flash. General-purpose computers have powerful CPUs, large RAM and an OS (Windows, macOS, Linux) that can install and run a wide range of applications.
Answer
Embedded: dedicated to one task, built into another device, minimal user interface (washing machine controller). General-purpose: runs many programs via an OS (laptop).
Examiner tip
A comparison needs a contrast for each point — give the embedded property AND the general-purpose counterpart. Listing only embedded features caps you at half marks.
Question
A computer uses three buses to move signals between the CPU and main memory. Name the three buses and, for each, state what it carries. (4 marks)
Step-by-step solution
Step 1
Address bus (1–2 marks). Carries memory ADDRESSES from the CPU to memory so a specific location can be selected. It is UNIDIRECTIONAL (CPU → memory). A wider address bus can address more memory locations.
Step 2
Data bus (1–2 marks). Carries the actual DATA or INSTRUCTIONS between the CPU and memory. It is BIDIRECTIONAL because data is both read from and written to memory.
Step 3
Control bus (1 mark). Carries CONTROL SIGNALS (e.g. read, write, interrupt, clock) that coordinate the components. It is bidirectional.
Answer
Address bus — carries memory addresses (CPU → memory, one-way). Data bus — carries data/instructions (two-way). Control bus — carries control signals such as read/write (two-way).
Examiner tip
1 mark per bus named with its content; the 4th mark is for a correct extra detail (direction, or 'wider address bus = more addressable memory'). Saying 'the data bus carries addresses' loses the data-bus mark.
Question
Describe the steps involved in the fetch-decode-execute (FDE) cycle. Refer to specific registers and buses in your answer. (6 marks)
Step-by-step solution
Step 1
Fetch — address transfer (1 mark). The Program Counter (PC) holds the address of the next instruction. The address is copied from the PC to the MAR (Memory Address Register).
Step 2
Fetch — instruction transfer (1 mark). The address is sent down the address bus to memory. The instruction at that address is sent back along the data bus and stored in the MDR (Memory Data Register), then copied to the CIR (Current Instruction Register).
Step 3
Increment PC (1 mark). The PC is incremented so it points to the next instruction (often during the fetch stage in parallel with the transfer).
Step 4
Decode (2 marks). The Control Unit (CU) decodes the instruction in the CIR — it interprets the opcode and operand to determine what action is required and which components are needed.
Step 5
Execute (1 mark). The CU sends control signals to the ALU and other components to perform the operation (e.g. arithmetic, logical, data movement). Results may be stored in the accumulator (ACC) or written back to memory.
Answer
Fetch: PC → MAR → address bus → memory → data bus → MDR → CIR; PC++. Decode: CU interprets the opcode in the CIR. Execute: CU signals the ALU/registers to perform the operation; result stored.
Examiner tip
Top-band answers name registers (PC, MAR, MDR, CIR, ACC) and buses (address, data, control). 'It gets the instruction and runs it' scores 1 mark at most.
Question
Identify and explain THREE factors that affect the performance of a CPU. (6 marks)
Step-by-step solution
Step 1
Clock speed (2 marks). Measured in Hz (typically GHz). Each clock cycle drives one instruction step; a higher clock speed means more cycles per second, so more instructions can be processed per second.
Step 2
Number of cores (2 marks). Each core can execute its own FDE cycle. A dual-core / quad-core / octa-core CPU can run multiple instructions simultaneously, increasing throughput — provided the software is multi-threaded.
Step 3
Cache size (2 marks). Cache is fast, on-chip memory holding frequently-used instructions and data. Larger cache reduces trips to slower main memory (RAM), so the CPU spends less time waiting and more time executing.
Answer
Clock speed (cycles/sec), number of cores (parallelism), cache size (memory-access latency). All three move the bottleneck somewhere else; well-balanced systems address all three.
Examiner tip
Each factor needs naming + an EFFECT (the 'so...' clause) for the second mark. Three named factors with no explanation scores only 3 of 6.
High-scoring sample answers for computer architecture on the Cambridge IGCSE 0478 paper, with examiner-style notes mapping each response to the mark scheme and assessment objectives.
State the purpose of the ALU within the CPU. (1 mark)
Model answer
The ALU (Arithmetic and Logic Unit) carries out the arithmetic operations (e.g. addition, subtraction) and logical operations (e.g. AND, OR, NOT, comparisons) on data inside the CPU.
Why this scores
AO1 (knowledge). 1 mark for arithmetic or logic operations correctly described. Naming the unit alone ('it's the Arithmetic and Logic Unit') without saying what it does does not earn the mark.
Describe the purpose of the accumulator (ACC) register. (2 marks)
Model answer
The accumulator is a register inside the CPU (1) that temporarily holds the result of the arithmetic and logical operations carried out by the ALU (1). Data is held there before it is written back to memory or used in the next operation.
Why this scores
AO1. 1 mark — a register / fast storage inside the CPU; 1 mark — holds the result of ALU (arithmetic/logic) operations. 'Stores data' alone is too vague for the second mark.
A computer uses the von Neumann model. Describe what is meant by the von Neumann architecture. (3 marks)
Model answer
In the von Neumann architecture a single CPU (control unit, ALU and registers) processes instructions (1). Both program instructions and data are stored together in the SAME main memory (1) and are accessed using the same shared buses (1). The CPU then runs the stored program one instruction at a time using the fetch–decode–execute cycle (also creditable).
Why this scores
AO1. 1 mark — single CPU/processor with control unit, ALU, registers; 1 mark — instructions and data stored in the same memory (the 'stored program' concept); 1 mark — shared buses / sequential execution via the FDE cycle. Max 3 from these points.
Explain the role of the Control Unit (CU) during the fetch–decode–execute cycle. (4 marks)
Model answer
The Control Unit manages and coordinates the activity of the CPU (1). It decodes the instruction held in the Current Instruction Register, interpreting the opcode to work out which operation is required (1). It then sends out control signals along the control bus to the other components — the ALU, registers and memory — telling them what to do and when (1). It also controls the timing of operations using the clock and manages the flow of data into and out of the CPU so each step happens in the correct sequence (1).
Why this scores
AO1/AO2. Award 1 mark each (max 4) for: coordinates CPU activity; decodes/interprets the instruction; sends control signals via the control bus; controls timing/synchronisation (clock) or directs data flow between components.
Describe the stages of the fetch–decode–execute cycle, referring to the registers and buses used. (5 marks)
Model answer
Fetch: The address of the next instruction is copied from the Program Counter (PC) to the Memory Address Register (MAR) (1). This address is sent along the address bus to main memory, and the instruction at that location is returned along the data bus into the Memory Data Register (MDR) and copied to the Current Instruction Register (CIR) (1). The PC is then incremented so it points to the next instruction (1). Decode: The Control Unit decodes the instruction in the CIR, interpreting the opcode and operand to determine the operation required (1). Execute: The Control Unit sends control signals so the ALU/registers carry out the operation, with any result stored in the accumulator or written back to memory (1).
Why this scores
AO1/AO2. Up to 5 from: PC→MAR; address bus → memory → data bus → MDR → CIR; increment PC; CU decodes opcode in CIR; execute via ALU with result in accumulator. Naming registers and buses is required for the top marks.
Explain how clock speed, the number of cores and cache size each affect the performance of a CPU. (6 marks)
Model answer
Clock speed: The clock speed (measured in Hz/GHz) is the number of cycles the CPU performs per second (1); a higher clock speed means more instructions can be fetched/executed per second, so the CPU works faster (1). Number of cores: Each core can run its own fetch–decode–execute cycle (1); with more cores the CPU can process several instructions at the same time (in parallel), increasing throughput — provided the software is written to use multiple cores/threads (1). Cache size: Cache is very fast memory close to the CPU that holds frequently-used instructions and data (1); a larger cache means more data can be kept near the CPU, reducing slow trips to main memory (RAM), so the CPU waits less and performs better (1).
Why this scores
AO1/AO2. 2 marks per factor (max 6): 1 for identifying/defining the factor, 1 for explaining its EFFECT on performance. The cores point should ideally note the software-dependency caveat; mark the explanation 'so...' clause, not just the term.
Definitions to memorise and the exact keywords mark schemes credit for computer architecture answers — sharpened from recent examiner reports for the 2026 0478 sitting.
The component that processes data and instructions. Made up of the ALU, control unit and registers.
Performs arithmetic operations (add, subtract) and logical operations (AND, OR, NOT, comparisons) within the CPU.
Decodes instructions and sends control signals to coordinate the activity of the CPU, memory and I/O devices.
A very small, very fast storage location inside the CPU. Holds data the CPU is currently working with.
Register that holds the memory address of the NEXT instruction to be fetched.
Register that holds the memory address of data or instructions currently being read from or written to memory.
Register that holds the data or instruction transferred between the CPU and memory.
Register that holds the instruction currently being decoded and executed.
Register that holds the result of arithmetic and logical operations.
A set of parallel wires that carries signals between CPU components. Three types: ADDRESS bus (memory addresses), DATA bus (data/instructions), CONTROL bus (control signals).
Architecture where instructions and data are stored in the SAME memory, accessed via the same buses, with the FDE cycle controlling execution.
The three-stage cycle the CPU follows for every instruction: FETCH it from memory, DECODE it in the control unit, EXECUTE it via the ALU/registers.
The number of cycles per second the CPU can perform, measured in hertz (Hz). Higher clock speed = more instructions per second.
An independent processing unit within a CPU. A multi-core CPU can run several instructions simultaneously.
Small, very fast memory inside (or close to) the CPU. Holds frequently-used data and instructions to reduce trips to slower main memory.
A computer built into another device that is dedicated to a specific task (e.g. washing machine controller, car ECU).
The traps other students keep falling into on computer architecture questions — taken from recent Cambridge IGCSE 0478 examiner reports and mark schemes — and how to avoid them.
0478 Examiner Reports 2022-2024
Why it happens
Students remember 'fetch, decode, execute' as three words but not the data-flow detail behind them.
How to avoid it
Always trace the address: PC → MAR → address bus → memory → data bus → MDR → CIR. The mark scheme rewards every named component and direction.
Why it happens
Marketing pushes GHz numbers as the headline.
How to avoid it
Clock speed is one factor. Cache, cores, RAM and storage type also matter. A 3.5 GHz dual-core may be slower than a 2.5 GHz octa-core for multi-threaded workloads.
Why it happens
Students think 'small computer = embedded'.
How to avoid it
Embedded systems are dedicated to a SPECIFIC task and built INTO another device. A smartphone runs many apps via an OS — it's general-purpose. A car's ECU IS embedded.
Why it happens
Both are 'buses' and both are involved in fetching instructions.
How to avoid it
ADDRESS bus carries the memory ADDRESS (one-way: CPU → memory). DATA bus carries the actual data/instruction (two-way). CONTROL bus carries signals (read, write, interrupt).
The things students keep getting wrong in this sub-topic, answered.