What is computer architecture in the context of Cambridge IGCSE Computer Science?

In the Cambridge IGCSE Computer Science curriculum, computer architecture refers to the design and organization of a computer's core components, including the central processing unit (CPU), memory, and input/output controls. It involves understanding how these components interact to execute instructions and process data efficiently.

How does the CPU function within computer architecture?

The CPU, or central processing unit, is the brain of the computer within the architecture. It performs calculations and executes instructions from programs by using its components: the arithmetic logic unit (ALU) for mathematical operations, the control unit (CU) for directing operations, and registers for temporary data storage. Understanding the CPU's role is crucial for grasping how computers process information.

What is the significance of the fetch-decode-execute cycle in computer architecture?

The fetch-decode-execute cycle is a fundamental concept in computer architecture that describes how the CPU processes instructions. During this cycle, the CPU fetches an instruction from memory, decodes it to understand the required action, and then executes it. This cycle is repeated continuously, allowing the computer to perform tasks efficiently and is a key topic in the Cambridge IGCSE Computer Science syllabus.

How do memory and storage differ in computer architecture?

In computer architecture, memory refers to the temporary storage used by the CPU to hold data and instructions that are actively being processed, such as RAM (Random Access Memory). Storage, on the other hand, refers to the permanent storage of data, such as hard drives or SSDs, where data is saved long-term. Understanding the difference is essential for students studying hardware in the Cambridge IGCSE Computer Science course.

What role do buses play in computer architecture?

Buses in computer architecture are crucial for data transfer between the CPU, memory, and other components. They are pathways that carry data, addresses, and control signals. There are different types of buses, such as data buses, address buses, and control buses, each serving a specific function in ensuring efficient communication within the computer system. This concept is an integral part of the Cambridge IGCSE Computer Science curriculum.

Why is "Describing the FDE cycle without naming registers or buses" a common mistake in Computer Architecture?

Why it happens: Students remember 'fetch, decode, execute' as three words but not the data-flow detail behind them. How to avoid it: Always trace the address: PC → MAR → address bus → memory → data bus → MDR → CIR. The mark scheme rewards every named component and direction. Source: 0478 Examiner Reports 2022-2024

Why is "Claiming a higher clock speed always means a faster computer" a common mistake in Computer Architecture?

Why it happens: Marketing pushes GHz numbers as the headline. How to avoid it: Clock speed is one factor. Cache, cores, RAM and storage type also matter. A 3.5 GHz dual-core may be slower than a 2.5 GHz octa-core for multi-threaded workloads.

Why is "Calling a smartphone or tablet an embedded system" a common mistake in Computer Architecture?

Why it happens: Students think 'small computer = embedded'. How to avoid it: Embedded systems are dedicated to a SPECIFIC task and built INTO another device. A smartphone runs many apps via an OS — it's general-purpose. A car's ECU IS embedded.

Why is "Confusing the data bus and address bus" a common mistake in Computer Architecture?

Why it happens: Both are 'buses' and both are involved in fetching instructions. How to avoid it: ADDRESS bus carries the memory ADDRESS (one-way: CPU → memory). DATA bus carries the actual data/instruction (two-way). CONTROL bus carries signals (read, write, interrupt).

HardwareCambridge IGCSE Computer Science (0478)

Computer Architecture

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Computer Architecture Study Notes — Cambridge IGCSE Computer Science 0478 (2026-2028 syllabus)

What's INSIDE a CPU and how it actually runs your programs. ALU, control unit, registers and buses; the Von Neumann model; the fetch-decode-execute cycle; what makes one CPU faster than another; and where embedded systems differ.

What you’ll learn

Mapped to the Cambridge IGCSE 0478 syllabus (2026-2028).

1.3.1 — Identify the main components of the CPU.
1.3.2 — Describe the role of the ALU, control unit and registers.
1.3.3 — Describe the Von Neumann architecture.
1.3.4 — Explain the fetch-decode-execute cycle.
1.3.5 — Identify factors affecting CPU performance.
1.3.6 — Describe embedded systems and contrast with general-purpose computers.

The parts of a CPU

ALU does the maths; control unit conducts; registers hold the working values.

The Central Processing Unit (CPU) is the brain of the computer. It has three main parts.

1. ALU (Arithmetic and Logic Unit). Does the actual computation:

Arithmetic: ADD, SUBTRACT, MULTIPLY, DIVIDE.
Logical: AND, OR, NOT, comparisons (>, <, =).

2. Control Unit (CU). Conducts the orchestra:

Decodes instructions.
Sends control signals along the control bus to coordinate the other components.
Manages the FDE cycle.

3. Registers. Tiny, super-fast storage locations inside the CPU. Each has a specific role:

Register	Role
PC (Program Counter)	Address of the NEXT instruction.
MAR (Memory Address Register)	Holds the address being read/written.
MDR (Memory Data Register)	Holds the data/instruction transferred.
CIR (Current Instruction Register)	Holds the instruction being decoded/executed.
ACC (Accumulator)	Holds the result of arithmetic/logic.

Cambridge tip. Examiner reports flag candidates who write 'memory' when they should write 'register'. They are different: registers are INSIDE the CPU and orders of magnitude faster than RAM.

ALU = arithmetic + logic.
CU decodes and signals.
Registers are CPU-local fast storage.
PC, MAR, MDR, CIR, ACC — know them.

Von Neumann architecture

Instructions and data share the same memory and the same buses.

Almost every general-purpose computer follows the Von Neumann architecture. The key idea: instructions and data are stored in the SAME main memory and accessed via the SAME buses.

The buses (the wires that move signals around):

Address bus — carries the memory address being accessed (one-way: CPU → memory).
Data bus — carries the actual data or instruction (two-way).
Control bus — carries timing and control signals (read, write, interrupt, clock).

Why this design wins. It's flexible — the same memory holds your operating system, your spreadsheet's code AND the spreadsheet's data. Programs can be loaded, modified and replaced without redesigning the hardware.

The downside ('Von Neumann bottleneck'). Because instructions and data share one bus, the CPU sometimes has to wait. Modern CPUs hide this with caches and pipelining (more on those below).

Cambridge tip. Mark scheme rewards naming the THREE buses and stating that instructions and data share memory.

Single shared memory for instructions + data.
Address, data, control buses.
Flexible; bottleneck mitigated by cache.

The fetch-decode-execute cycle

Three stages, repeated billions of times per second.

Every instruction the CPU executes goes through three stages — the fetch-decode-execute (FDE) cycle.

FETCH.

The PC holds the address of the next instruction. The address is copied to the MAR.
The address is sent down the address bus to memory.
The instruction at that address is sent back along the data bus to the MDR.
The instruction is then copied to the CIR.
The PC is incremented to point to the NEXT instruction.

DECODE. The control unit decodes the instruction in the CIR — interprets the opcode and operand to figure out what action is needed and which components to involve.

EXECUTE. The control unit signals the ALU and registers to perform the operation. The result may be stored in the accumulator or written back to memory (which would trigger another address-and-data-bus exchange).

The cycle then repeats — billions of times per second on a modern CPU.

Cambridge tip. Top-band answers walk through the buses and registers explicitly. 'It fetches the instruction and runs it' scores 1 of 6.

Fetch: PC → MAR → memory → MDR → CIR; PC++.
Decode: CU interprets the CIR.
Execute: ALU acts; result possibly stored.

See the full worked example for computer architecture →

What makes one CPU faster than another

Three big levers: clock speed, cores, cache.

A CPU's performance depends on more than one factor. The big three:

Clock speed. Measured in hertz (Hz, GHz). One full clock cycle drives one step of the FDE cycle. Higher clock speed = more instructions per second, all else being equal.

Number of cores. Each core is a self-contained processor that can run its own FDE cycle. A quad-core CPU can run FOUR programs simultaneously, or split a multi-threaded program across cores. (Single-threaded programs only see one core's worth of speed.)

Cache size. Cache is fast on-chip memory holding frequently-used data and instructions. Trips to cache take a single cycle; trips to RAM take dozens. More cache = fewer waits.

Other factors.

Word size — number of bits the CPU processes at once (32-bit vs 64-bit).
Bus widths — how many bits move at a time.
Architecture / instruction set — same clock speed can mean different real-world speed across CPU families.

Why this matters in real life. A 3.5 GHz dual-core can be SLOWER than a 2.5 GHz octa-core for software designed to use multiple threads (video editing, modern games). When buying a computer, balance all three.

Clock speed — cycles per second.
Cores — parallel processing capacity.
Cache — fast on-chip memory reduces RAM trips.

See the full worked example for computer architecture →

Embedded systems vs general-purpose computers

Embedded = dedicated to one job, built into another device.

An embedded system is a computer built into a larger device, dedicated to a SPECIFIC task. The user usually doesn't think of it as a 'computer' at all.

Examples of embedded systems:

Washing-machine controller (cycles, water level, temperature).
Car engine management unit (ECU).
Microwave oven keypad and timer.
Digital camera image processor.
Smart-thermostat / heating controller.
Fitness tracker.

Compared to a general-purpose computer:

	Embedded system	General-purpose
Purpose	One specific task	Runs many programs
Hardware	Microcontroller, low power, low cost	Powerful CPU, lots of RAM
Software	Firmware in ROM/flash	OS + many applications
User interaction	Limited (buttons, dials, display)	Keyboard, mouse, screen
Updates	Rare; via service intervention	Frequent; user-initiated

The key word is DEDICATED. A smartphone runs many apps via an OS — it's general-purpose. A car ECU only runs the engine code — embedded.

Cambridge tip. Mark scheme expects students to say 'designed for a specific task / dedicated' and 'built into another device'.

Dedicated to one task.
Built into another device.
Cheaper, lower-power microcontrollers.
Firmware in ROM/flash, rarely updated.

See the full worked example for computer architecture →

How it’s examined

Computer architecture appears on roughly half of Paper 1s. Most-tested questions: describe the FDE cycle (6-8 marks), factors affecting CPU performance (4-6 marks), embedded vs general-purpose (4-6 marks). Examiner reports flag the FDE cycle as the question candidates lose most marks on — for vagueness rather than wrong answers.

Sources: Cambridge IGCSE Computer Science 0478 syllabus (2026-2028); 0478 Examiner Reports 2022-2024; 0478/12 Oct/Nov 2023 question paper and mark scheme. Last reviewed 2026-05-09.

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Step-by-step worked examples — Computer Architecture

Step-by-step solutions to past-paper-style questions on computer architecture, written exactly the way a tutor would explain them at the board.

1Describe the fetch-decode-execute cycle (6 marks)
Extended• Adapted from 0478/12 Oct/Nov 2023 Q9• fde, cpu
Question
Describe the steps involved in the fetch-decode-execute (FDE) cycle. Refer to specific registers and buses in your answer. (6 marks)
Step-by-step solution
1. Step 1
  Fetch — address transfer (1 mark). The Program Counter (PC) holds the address of the next instruction. The address is copied from the PC to the MAR (Memory Address Register).
2. Step 2
  Fetch — instruction transfer (1 mark). The address is sent down the address bus to memory. The instruction at that address is sent back along the data bus and stored in the MDR (Memory Data Register), then copied to the CIR (Current Instruction Register).
3. Step 3
  Increment PC (1 mark). The PC is incremented so it points to the next instruction (often during the fetch stage in parallel with the transfer).
4. Step 4
  Decode (2 marks). The Control Unit (CU) decodes the instruction in the CIR — it interprets the opcode and operand to determine what action is required and which components are needed.
5. Step 5
  Execute (1 mark). The CU sends control signals to the ALU and other components to perform the operation (e.g. arithmetic, logical, data movement). Results may be stored in the accumulator (ACC) or written back to memory.
Answer
Fetch: PC → MAR → address bus → memory → data bus → MDR → CIR; PC++. Decode: CU interprets the opcode in the CIR. Execute: CU signals the ALU/registers to perform the operation; result stored.
Examiner tip
Top-band answers name registers (PC, MAR, MDR, CIR, ACC) and buses (address, data, control). 'It gets the instruction and runs it' scores 1 mark at most.
2Factors affecting CPU performance (6 marks)
Extended• cpu, performance
Question
Identify and explain THREE factors that affect the performance of a CPU. (6 marks)
Step-by-step solution
1. Step 1
  Clock speed (2 marks). Measured in Hz (typically GHz). Each clock cycle drives one instruction step; a higher clock speed means more cycles per second, so more instructions can be processed per second.
2. Step 2
  Number of cores (2 marks). Each core can execute its own FDE cycle. A dual-core / quad-core / octa-core CPU can run multiple instructions simultaneously, increasing throughput — provided the software is multi-threaded.
3. Step 3
  Cache size (2 marks). Cache is fast, on-chip memory holding frequently-used instructions and data. Larger cache reduces trips to slower main memory (RAM), so the CPU spends less time waiting and more time executing.
Answer
Clock speed (cycles/sec), number of cores (parallelism), cache size (memory-access latency). All three move the bottleneck somewhere else; well-balanced systems address all three.
3Embedded vs general-purpose computers (4 marks)
Core• embedded
Question
Compare an embedded system with a general-purpose computer. Give one example of each. (4 marks)
Step-by-step solution
1. Step 1
  Purpose (2 marks). An embedded system is designed for a SPECIFIC task and is built into a larger device — e.g. the controller in a washing machine, the system in a digital camera, the engine management unit in a car. A general-purpose computer can run many DIFFERENT programs — e.g. a desktop PC, a laptop.
2. Step 2
  Hardware/software trade-off (2 marks). Embedded systems use cheaper, lower-power microcontrollers; their firmware is fixed (or rarely updated) and lives in ROM/flash. General-purpose computers have powerful CPUs, large RAM and an OS (Windows, macOS, Linux) that can install and run a wide range of applications.
Answer
Embedded: dedicated to one task, built into another device, minimal user interface (washing machine controller). General-purpose: runs many programs via an OS (laptop).

Key Definitions and Keywords — Computer Architecture

Definitions to memorise and the exact keywords mark schemes credit for computer architecture answers — sharpened from recent examiner reports for the 2026 0478 sitting.

CPU (Central Processing Unit)
Examiner keyword
The component that processes data and instructions. Made up of the ALU, control unit and registers.
ALU (Arithmetic and Logic Unit)
Examiner keyword
Performs arithmetic operations (add, subtract) and logical operations (AND, OR, NOT, comparisons) within the CPU.
Control Unit (CU)
Examiner keyword
Decodes instructions and sends control signals to coordinate the activity of the CPU, memory and I/O devices.
Register
Examiner keyword
A very small, very fast storage location inside the CPU. Holds data the CPU is currently working with.
Program Counter (PC)
Examiner keyword
Register that holds the memory address of the NEXT instruction to be fetched.
MAR (Memory Address Register)
Examiner keyword
Register that holds the memory address of data or instructions currently being read from or written to memory.
MDR (Memory Data Register)
Examiner keyword
Register that holds the data or instruction transferred between the CPU and memory.
CIR (Current Instruction Register)
Examiner keyword
Register that holds the instruction currently being decoded and executed.
Accumulator (ACC)
Register that holds the result of arithmetic and logical operations.
Bus
Examiner keyword
A set of parallel wires that carries signals between CPU components. Three types: ADDRESS bus (memory addresses), DATA bus (data/instructions), CONTROL bus (control signals).
Von Neumann architecture
Examiner keyword
Architecture where instructions and data are stored in the SAME memory, accessed via the same buses, with the FDE cycle controlling execution.
Fetch-decode-execute (FDE) cycle
Examiner keyword
The three-stage cycle the CPU follows for every instruction: FETCH it from memory, DECODE it in the control unit, EXECUTE it via the ALU/registers.
Clock speed
Examiner keyword
The number of cycles per second the CPU can perform, measured in hertz (Hz). Higher clock speed = more instructions per second.
Core
Examiner keyword
An independent processing unit within a CPU. A multi-core CPU can run several instructions simultaneously.
Cache
Examiner keyword
Small, very fast memory inside (or close to) the CPU. Holds frequently-used data and instructions to reduce trips to slower main memory.
Embedded system
Examiner keyword
A computer built into another device that is dedicated to a specific task (e.g. washing machine controller, car ECU).

Common Mistakes and Misconceptions — Computer Architecture

The traps other students keep falling into on computer architecture questions — taken from recent Cambridge IGCSE 0478 examiner reports and mark schemes — and how to avoid them.

✕Describing the FDE cycle without naming registers or buses
0478 Examiner Reports 2022-2024
Why it happens
Students remember 'fetch, decode, execute' as three words but not the data-flow detail behind them.
How to avoid it
Always trace the address: PC → MAR → address bus → memory → data bus → MDR → CIR. The mark scheme rewards every named component and direction.
✕Claiming a higher clock speed always means a faster computer
Why it happens
Marketing pushes GHz numbers as the headline.
How to avoid it
Clock speed is one factor. Cache, cores, RAM and storage type also matter. A 3.5 GHz dual-core may be slower than a 2.5 GHz octa-core for multi-threaded workloads.
✕Calling a smartphone or tablet an embedded system
Why it happens
Students think 'small computer = embedded'.
How to avoid it
Embedded systems are dedicated to a SPECIFIC task and built INTO another device. A smartphone runs many apps via an OS — it's general-purpose. A car's ECU IS embedded.
✕Confusing the data bus and address bus
Why it happens
Both are 'buses' and both are involved in fetching instructions.
How to avoid it
ADDRESS bus carries the memory ADDRESS (one-way: CPU → memory). DATA bus carries the actual data/instruction (two-way). CONTROL bus carries signals (read, write, interrupt).

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Computer Architecture

Short Study Notes in the form of Slides

Detailed Study Notes

What you’ll learn

How it’s examined

1Describe the fetch-decode-execute cycle (6 marks)

2Factors affecting CPU performance (6 marks)

3Embedded vs general-purpose computers (4 marks)

CPU (Central Processing Unit)

ALU (Arithmetic and Logic Unit)

Control Unit (CU)

Register

Program Counter (PC)

MAR (Memory Address Register)

MDR (Memory Data Register)

CIR (Current Instruction Register)

Accumulator (ACC)

Bus

Von Neumann architecture

Fetch-decode-execute (FDE) cycle

Clock speed

Core

Cache

Embedded system

✕Describing the FDE cycle without naming registers or buses

✕Claiming a higher clock speed always means a faster computer

✕Calling a smartphone or tablet an embedded system

✕Confusing the data bus and address bus

Practice questions

Past paper style quiz

Assess your understanding

Computer Architecture — frequently asked questions