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Detailed notes on Boolean logic for Cambridge IGCSE Computer Science, covering key concepts, explanations, examples, and exam-focused revision points.
Six logic gates — AND, OR, NOT, NAND, NOR, XOR — and their truth tables. The building blocks every digital circuit (and ultimately every CPU instruction) is made from.
Mapped to the Cambridge IGCSE 0478 syllabus (2026-2028).
Three gates that do everything else can be built from.
AND gate. Output is 1 ONLY when BOTH (or all) inputs are 1.
| A | B | A AND B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Real-world example: 'Coffee maker turns on when (water tank is full) AND (power switch is on)'.
OR gate. Output is 1 if AT LEAST ONE input is 1.
| A | B | A OR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Real-world example: 'Doorbell rings when (front door pressed) OR (back door pressed)'.
NOT gate. SINGLE input. Output INVERTS the input.
| A | NOT A |
|---|---|
| 0 | 1 |
| 1 | 0 |
Real-world example: 'Light comes on when it is NOT daytime'.
Cambridge tip. Always show truth tables row-by-row. Mark scheme awards method marks even for partial answers.
NAND and NOR are universal; XOR detects difference.
NAND gate. AND followed by NOT. Output is 1 unless BOTH inputs are 1.
| A | B | A NAND B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
NOR gate. OR followed by NOT. Output is 1 ONLY when BOTH inputs are 0.
| A | B | A NOR B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Universal gates. NAND alone (or NOR alone) can implement ANY logic function. CPU manufacturers use this fact — circuits made from a single gate type are simpler to manufacture.
XOR gate. Output is 1 when inputs DIFFER (exactly one is 1).
| A | B | A XOR B |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Used in: ADDERS (the carry-propagation logic), parity bits, error detection (covered in Topic 3).
Cambridge tip. Mark scheme distinguishes OR from XOR by the (1,1) row. Memorise it — that's the test.
Every digital decision is gates working together.
Logic gates appear everywhere in computer systems and electronics.
Inside a CPU. All arithmetic and logic operations (the ALU's job) are implemented using combinations of AND, OR, NOT, XOR. A 1-bit full adder is just a couple of XORs, a couple of ANDs and an OR.
Memory cells. Latches and flip-flops (the building blocks of RAM cells) are NAND or NOR gates wired in feedback loops.
Decoders and multiplexers. Address decoders in memory chips use AND gates to select the right cell. Multiplexers select between inputs using AND/OR combinations.
Real-world examples.
Cambridge tip. When a question gives a real-world scenario, BREAK IT DOWN into individual conditions then identify the gates connecting them.
Verbatim phrases and definitions Cambridge mark schemes credit.
Logic gates appear on every Paper 2. Most-tested questions: complete a truth table (6-8 marks), identify gates from descriptions (4-6 marks), apply gates to a real-world scenario (6-8 marks). Examiner reports flag confusion between OR and XOR as the most common error.
Sources: Cambridge IGCSE Computer Science 0478 syllabus (2026-2028); 0478 Examiner Reports 2022-2024; 0478/22 Oct/Nov 2024 question paper and mark scheme. Last reviewed 2026-05-09.
Step-by-step solutions to past-paper-style questions on standard logic gates, written exactly the way a tutor would explain them at the board.
Question
Complete the truth table for a 2-input AND gate. The input columns A and B are already filled with all four combinations; give the output column X. (2 marks)
Step-by-step solution
Step 1
Recall the rule. An AND gate outputs 1 ONLY when ALL of its inputs are 1. With two inputs that means only the row A = 1, B = 1.
Step 2
Fill each row in order 00, 01, 10, 11. 0 AND 0 = 0; 0 AND 1 = 0; 1 AND 0 = 0; 1 AND 1 = 1. So the output column is 0, 0, 0, 1.
Answer
| A | B | X (A AND B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Examiner tip
Two inputs ALWAYS give four rows (2² = 4). Only the final row scores the '1' — a single wrong 1 elsewhere is the most common slip. AO2 (apply the gate rule).
Question
Complete the truth table for a 2-input OR gate. Give the output column X for the four input combinations. (2 marks)
Step-by-step solution
Step 1
Recall the rule. An OR gate outputs 1 when AT LEAST ONE input is 1 — including when both are 1. It outputs 0 only when every input is 0.
Step 2
Fill each row. 0 OR 0 = 0; 0 OR 1 = 1; 1 OR 0 = 1; 1 OR 1 = 1. So the output column is 0, 1, 1, 1.
Answer
| A | B | X (A OR B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Examiner tip
Watch the 1,1 row: OR gives 1 there (this is what distinguishes OR from XOR). Only the 0,0 row gives 0. AO2.
Question
Complete a single truth table showing the output of A AND B, A OR B and A XOR B for all combinations of A and B. (4 marks)
Step-by-step solution
Step 1
Set up the rows. Four rows for A and B: 00, 01, 10, 11. Add one output column per gate.
Step 2
AND column. Output 1 ONLY when BOTH inputs are 1 → 0, 0, 0, 1.
Step 3
OR column. Output 1 when AT LEAST ONE input is 1 → 0, 1, 1, 1.
Step 4
XOR column. Output 1 when EXACTLY ONE input is 1 (the inputs DIFFER) → 0, 1, 1, 0. Note this matches OR except the 1,1 row, which is 0.
Answer
| A | B | AND | OR | XOR |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 |
| 1 | 0 | 0 | 1 | 1 |
| 1 | 1 | 1 | 1 | 0 |
Examiner tip
Lining the three gates up in one table makes the OR-vs-XOR difference obvious: identical except the bottom row. AO2 — apply three gate rules accurately.
Question
Describe the operation of the NOT, NAND and NOR gates, stating the number of inputs of each. State the relationship between NAND and AND, and between NOR and OR. (4 marks)
Step-by-step solution
Step 1
NOT. A SINGLE-INPUT gate that INVERTS its input: NOT 0 = 1; NOT 1 = 0. Its symbol is a triangle with a small circle on the output.
Step 2
NAND (2 inputs). Equivalent to an AND gate followed by a NOT — i.e. NOT (A AND B). Output is 1 unless BOTH inputs are 1, giving 1, 1, 1, 0 for 00, 01, 10, 11.
Step 3
NOR (2 inputs). Equivalent to an OR gate followed by a NOT — i.e. NOT (A OR B). Output is 1 ONLY when BOTH inputs are 0, giving 1, 0, 0, 0.
Answer
NOT (1 input) inverts. NAND (2 inputs) = NOT(AND): output 1, 1, 1, 0. NOR (2 inputs) = NOT(OR): output 1, 0, 0, 0. NAND and NOR are the 'universal gates' — any logic circuit can be built using only NANDs, or only NORs.
Examiner tip
Each NAND/NOR truth table is the AND/OR table with every bit flipped — a fast check. State the input count explicitly: NOT is the only single-input gate. AO1 (recall) + AO2.
Question
A 2-input gate has the truth table below. Identify the gate and justify your choice.
| A | B | X |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
| (3 marks) |
Step-by-step solution
Step 1
Look at where the output is 1. The output is 1 in exactly one row — when A = 0 AND B = 0 — and 0 everywhere else.
Step 2
Eliminate look-alikes. A NOT gate is ruled out because there are two inputs. 'Output 1 only when both inputs are 0' is the OR rule inverted.
Step 3
Confirm. OR gives 0, 1, 1, 1; inverting every bit gives 1, 0, 0, 0 — which matches. So this is a NOR gate.
Answer
The gate is a NOR gate: it outputs 1 only when all inputs are 0, which is NOT(A OR B) — the inverse of the OR table.
Examiner tip
Strategy: scan the output column for the pattern of 1s. A single 1 in the 0,0 row ⇒ NOR; a single 0 in the 1,1 row ⇒ NAND. Do NOT confuse NOR (one 1) with NAND (three 1s). AO3 (analyse/deduce).
Question
Complete the truth table for a 2-input XOR gate and explain, with reference to the table, how XOR differs from OR. (3 marks)
Step-by-step solution
Step 1
XOR rule. XOR (exclusive OR) outputs 1 when EXACTLY ONE input is 1 — i.e. when the inputs differ. When the inputs are the SAME (both 0 or both 1) the output is 0.
Step 2
Fill the rows. 0 XOR 0 = 0; 0 XOR 1 = 1; 1 XOR 0 = 1; 1 XOR 1 = 0 → 0, 1, 1, 0.
Step 3
Compare with OR. OR gives 0, 1, 1, 1. The only difference is the A = 1, B = 1 row: OR outputs 1 (at least one input is 1), but XOR outputs 0 (the inputs are not different).
Answer
| A | B | X (A XOR B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
XOR and OR agree on the first three rows but differ on the 1,1 row: OR = 1, XOR = 0. XOR is true only when the inputs are different.
Examiner tip
The 1,1 row is the entire difference between OR and XOR — the most-penalised confusion in this topic. XOR is the basis of binary adders and parity checks. AO2 + AO3.
High-scoring sample answers for standard logic gates on the Cambridge IGCSE 0478 paper, with examiner-style notes mapping each response to the mark scheme and assessment objectives.
A NOT gate has the input A = 1. State the output of the gate. [1 mark]
Model answer
Output = 0. (A NOT gate inverts its single input: NOT 1 = 0.)
Why this scores
1 mark for 0. The trap is treating NOT as if it had two inputs — it has exactly one. AO1 (recall of the NOT gate function).
Complete the truth table for a 2-input AND gate. [2 marks]
| A | B | X |
|---|---|---|
| 0 | 0 | |
| 0 | 1 | |
| 1 | 0 | |
| 1 | 1 |
Model answer
| A | B | X (A AND B) |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Why this scores
1 mark for the three 0s in the top rows, 1 mark for the 1 in the 1,1 row. AND outputs 1 only when both inputs are 1 — do not award if any other row is set to 1. AO2.
A student tests a 2-input gate and records the truth table below. Identify the gate. [3 marks]
| A | B | X |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Model answer
The gate is an OR gate. The output is 1 whenever at least one input is 1 (rows 01, 10, 11) and only 0 when both inputs are 0. This is the OR truth table — and the 1,1 row being 1 rules out XOR (which would give 0 there).
Why this scores
1 mark: identify OR. 1 mark: 'output 1 when at least one input is 1'. 1 mark: justify by the 1,1 row distinguishing it from XOR. Common error: answering XOR — only correct if the 1,1 row were 0. AO3 (analyse a table) + AO1.
Complete the truth table for a 2-input NAND gate, and state its relationship to the AND gate. [4 marks]
| A | B | X |
|---|---|---|
| 0 | 0 | |
| 0 | 1 | |
| 1 | 0 | |
| 1 | 1 |
Model answer
| A | B | X (A NAND B) |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Relationship: a NAND gate is an inverted AND gate — its output is NOT(A AND B). Every output is the opposite of the corresponding AND output, so it is 1 unless both inputs are 1.
Why this scores
3 marks for the table (all four output bits 1, 1, 1, 0 — award 1 mark per pair correct as per mark scheme banding) and 1 mark for stating NAND = NOT(AND) / inverted AND. Trap: writing the NOR table (1, 0, 0, 0) instead — NAND has three 1s, NOR has one. AO2 + AO1.
Two gates, P and Q, have the truth tables below. Identify gate P and gate Q, and describe the one difference between them. [5 marks]
Gate P:
| A | B | X |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 1 |
Gate Q:
| A | B | X |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
Model answer
Gate P is an OR gate (output 1 when at least one input is 1; the 1,1 row is 1). Gate Q is an XOR gate (output 1 only when exactly one input is 1 — when the inputs differ; the 1,1 row is 0). Difference: the tables are identical except the A = 1, B = 1 row — OR gives 1 there because at least one input is 1, but XOR gives 0 there because the inputs are not different.
Why this scores
1 mark: P = OR. 1 mark: Q = XOR. 1 mark: OR = 1 when at least one input is 1. 1 mark: XOR = 1 only when exactly one input is 1 / inputs differ. 1 mark: the 1,1 row is the sole difference. This question targets the headline OR-vs-XOR confusion — swapping the two identifications scores 0 on the first two marks. AO3 (compare/analyse) + AO1.
Complete the truth tables for the NAND, NOR and XOR gates for all input combinations of A and B. [6 marks]
| A | B | NAND | NOR | XOR |
|---|---|---|---|---|
| 0 | 0 | |||
| 0 | 1 | |||
| 1 | 0 | |||
| 1 | 1 |
Model answer
| A | B | NAND | NOR | XOR |
|---|---|---|---|---|
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 0 |
Why this scores
2 marks per column (one slip in a column drops it to 1; two or more slips score 0 for that column). Key checks: NAND has three 1s and a single 0 in the 1,1 row; NOR has a single 1 in the 0,0 row; XOR has 1s only on the 'different' rows (01 and 10). Most-penalised errors: swapping the NAND and NOR columns, and giving XOR a 1 in the 1,1 row (that would be OR). AO2 — apply three gate rules accurately.
Definitions to memorise and the exact keywords mark schemes credit for standard logic gates answers — sharpened from recent examiner reports for the 2026 0478 sitting.
Two-input gate. Output is 1 ONLY when ALL inputs are 1. Truth table: 0, 0, 0, 1. Pseudocode: IF A AND B.
Two-input gate. Output is 1 if AT LEAST ONE input is 1 (including both). Truth table: 0, 1, 1, 1. Pseudocode: IF A OR B.
A SINGLE-INPUT gate that inverts the input. NOT 0 = 1; NOT 1 = 0. The only gate with one input.
Inverted AND — NOT(A AND B). Output is 1 unless ALL inputs are 1. Truth table: 1, 1, 1, 0. Universal gate — any circuit can be built from NANDs alone.
Inverted OR — NOT(A OR B). Output is 1 ONLY when ALL inputs are 0. Truth table: 1, 0, 0, 0. Universal gate.
Two-input gate. Output is 1 when inputs DIFFER (exactly one is 1). Truth table: 0, 1, 1, 0. Used in adders and parity circuits.
A table showing the output of a gate or circuit for every possible combination of inputs. n inputs give 2ⁿ rows.
The traps other students keep falling into on standard logic gates questions — taken from recent Cambridge IGCSE 0478 examiner reports and mark schemes — and how to avoid them.
0478 Examiner Reports 2022-2024
Why it happens
Both output 1 when 'at least one is 1', so the first three rows are identical.
How to avoid it
OR: 1 when AT LEAST ONE input is 1 (including BOTH). XOR: 1 when EXACTLY ONE input is 1 (NOT both). The 1,1 row is the only difference — OR = 1, XOR = 0.
0478 Examiner Reports 2022-2024
Why it happens
Both are 'inverted' gates, so students remember they have lots of 1s/0s but not which.
How to avoid it
NAND = NOT(AND): three 1s and a single 0 in the 1,1 row → 1, 1, 1, 0. NOR = NOT(OR): a single 1 in the 0,0 row → 1, 0, 0, 0. NAND has more 1s than NOR.
Why it happens
NAND IS conceptually that.
How to avoid it
In symbol form, NAND is drawn as the AND symbol with a small circle on the output. ONE GATE, not two.
Why it happens
Students forget the 11 row.
How to avoid it
Two inputs = 4 rows (00, 01, 10, 11). Three inputs = 8 rows. Always 2ⁿ rows.
Why it happens
Other gates have two inputs.
How to avoid it
NOT has ONE INPUT only — it inverts that single input. Never two-input.
The things students keep getting wrong in this sub-topic, answered.